module mul_wrapper(
  input clk,
  input rst,
  input [130:0] in_bundle,
  output [64:0] out_bundle
);

wire [31:0] a;
wire [31:0] b;
wire        sign;
wire        add;
wire [63:0] addend;
wire        valid;

wire [31:0] hi;
wire [31:0] lo;
wire        ready;

assign {valid, a, b, add, addend, sign} = in_bundle;
assign out_bundle = {ready, hi, lo};

mul u_mul(
  .i_clk(clk),
  .i_rst(rst),
  .i_a(a),
  .i_b(b),
  .i_sign(sign),
  .i_add(add),
  .i_addend(addend),
  .i_valid(valid),
  .o_hi(hi),
  .o_lo(lo),
  .o_ready(ready)
);

endmodule
